1. Field of Art
The disclosure generally relates to video compression, and more particularly, to implementing a cache management scheme in a context-adaptive binary arithmetic coding (CABAC) encoder with a dual-pipeline architecture in a video processing system.
2. Description of the Related Art
The H.264 video coding standard includes several algorithmic improvements upon previous block-oriented motion-compensation-based video codecs. One such improvement is the availability of multiple advanced entropy coding methods, such as CABAC encoding. CABAC is a high density implementation of entropy encoding, and is based on the key elements of binarization, context modeling and binary arithmetic coding. The usage of arithmetic coding and adaptive codes permits CABAC adaptation to non-stationary symbol statistics. Context modeling is applied to a binary sequence of the syntactical elements of the video data, such as block types, motion vectors, and quantized coefficients. Context modeling allows previously coded syntax elements to be used in estimating conditional probabilities, which in turn may be used in switching between estimated probability models to improve entropy coding efficiency.
The context models in CABAC are adaptive, and change over time depending on the values of received bins to be encoded. As context models are adapted for future use, updated context models must be stored during periods of non-use. As a result, context tables may be implemented in a CABAC encoder, typically with a single I/O-port memory. Single I/O port memories are limited in operation to either one memory read or one memory write in a given clock cycle, but not both. Thus, if a context table memory receives a context model read request and write request in the same clock cycle, a stall must be inserted in the CABAC encoder pipeline to accommodate both requests. This results in an increase in encoding latency, decreasing overall CABAC and H.264 performance.
The problem is compounded in dual-pipeline CABAC architectures, where each pipeline encodes a received bin in a given clock cycle. In such architectures, each pipeline may request a context model and may produce an updated context model in a given clock cycle. Two pipelines each requesting a context memory read and write may result in up to four context table access operations in one clock cycle, requiring as many as three pipeline stalls per operation. Without efficient context model management, this may decrease CABAC and H.264 performance by up to 75%.
The figures depict an embodiment for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein.